The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device including a capacitor using a cylindrical or a pillar-shaped storage electrode.
DRAM is a semiconductor memory device which each of the memory cells can be comprised of one transistor and one capacitor. Various structures of DRAM and methods for forming the structures have been conventionally studied to fabricate high density and highly integrated semiconductor storage devices. Especially a structure of the capacitor of DRAM much influences high integration, and it is important how to ensure a required storage capacitance without interfering with high integration of the device.
For high integration, it is essential to make a memory cell area small, and an area for a capacitor to be formed in is required to be small. Then, it is proposed that a capacitor including a pillar-shaped or cylindrical storage electrode is used, whereby the capacitor has a surface area increased height-wise so as to ensure a required storage capacitance without having a floor area increased.
A method for fabricating a conventional semiconductor device will be explained with reference to FIGS. 26A-26C and 27A-27B.
First, a memory cell transistor including a gate electrode 204 and source/drain diffused layers 206 is formed on a silicon substrate 200 in the same way as in the usual MOS transistor fabrication method (FIG. 26A).
Next, a silicon oxide film is deposited by, e.g., CVD (Chemical Vapor Deposition) method on the silicon substrate 200 with the memory cell transistor formed on, and then the surface of the silicon oxide film is polished by, CMP (Chemical Mechanical Polishing) method to form an inter-layer insulation film 208 which is formed of the silicon oxide film and has the surface planarized.
Then, a contact hole 210 is formed in the inter-layer insulation film 208 down to the source/drain diffused layer 206 by lithography and etching.
Next, a conducting film is deposited by, e.g., CVD method and is polished until the surface of the inter-layer insulation film 208 is exposed by, e.g., CMP method to form a plug 212 buried in the contact hole 210 (FIG. 26B).
Then, a silicon oxide film is deposited by, e.g., CVD method on the inter-layer insulation film 208 with the plug 212 buried in to form an inter-layer insulation film 214 of the silicon oxide film.
Next, an opening 216 exposing the plug 212 is formed in the inter-layer insulation film 214 by lithography and etching.
Then, a ruthenium film is deposited on the entire surface by, e.g., CVD method and polished by, e.g., CMP method until the surface of the inter-layer insulation film 214 is exposed to form a cylindrical storage electrode 218 of the ruthenium film formed on the inside wall and the bottom of the opening 216 (FIG. 26C).
Then, when the so-called cylindrical capacitor using the inside surface and the outside surface of the cylindrical storage electrode 218 is formed, the inter-layer insulation film 214 is removed selectively with respect to the inter-layer insulation film 208 to expose the outside surface of the storage electrode 218. Then, a capacitor dielectric film 220 of, e.g., Ta2O5 and a plate electrode 222 of, e.g., ruthenium film are deposited by, e.g., CVD method to form a capacitor constituted by the storage electrode 218, the capacitor dielectric film 220 and the plate electrode 222 (FIG. 27A).
Other wise, when the so-called concave capacitor using the inside surface of a cylindrical storage electrode is formed, a dielectric film 220 of, e.g., Ta2O5 and a plate electrode 222 of, e.g., ruthenium film are deposited by, e.g., CVD method without removing the inter-layer insulation film 214, and a capacitor constituted by the storage electrode 218, the capacitor dielectric film 220 and the plate electrode 222 is formed (FIG. 27B).
Thus, a DRAM including the capacitor using the cylindrical storage electrode is fabricated.
In the conventional semiconductor device fabrication method, the conducting film on the inter-layer insulation film 214 is removed by CMP method to form the storage electrode 218 selectively in the opening 216, and consequently, an edge as shown in FIG. 28A is formed on the upper end of the thus-formed storage electrode 218. Especially in a case that dishing takes place in polishing by CMP method, an acute edge as shown in FIG. 28B is formed on the upper end of the storage electrode 218 because a side of the storage electrode 218 near the inside surface is more polished than a side of the storage electrode 218 near the outside surface.
When an edge is thus formed on the upper end of the storage electrode 218, an electric field is concentrated on the edge to thereby often degrade drastically insulation of the capacitor dielectric film 220 in comparison with the insulation of the capacitor dielectric film having planar electrode. Especially when the edge is acutely angled, a large electric field is applied intensively on the edge, often causing dielectric breakdown to the capacitor dielectric film 220.